IDE3381 APOCAT – ROIC for high-rate, high-resolution x-ray and gamma-ray
spectroscopy with scintillators and PMTs or SiPMs, operating in space and for solar missions.

Product Description


IDE3381 APOCAT – the Array of Photon Counters Above Threshold is an integrated circuit (ASIC) for reading out up to 16 photomultiplier tubes (PMTs) and silicon photomultipliers (SiPMs). With scintillators, it is ideal for high-resolution x-ray and gamma-ray pulse-height spectroscopy, or photon timing and 4-bin energy resolved photon counting at high data rates up to 1Mcps per channel, synchronously or asynchronously per channel. The ASIC was originally designed for space missions, but thanks to on-chip ADC and versatile registers, it can be programmed for other use cases including low-power terrestrial applications with PMTs and SiPMs.”

General Description

The IDE3381 is an integrated circuit (IC) for the readout of photon detectors, e.g., photomultiplier tubes (PMTs), silicon photomultipliers (SiPMs). The IC has 16 channels and 1 summing channel. Each channel can be used for high-resolution pulse-height spectroscopy, timing and 4-bin energy resolved 18-bit counting. The readout was designed for relatively high rates of about 1Mcps per channel. The channels can operate synchronously or asynchronously. The channel is programmable for peaking time of 50 ns, 150 ns, 300 ns, or 2000 ns to allow for pulse-height spectroscopy using various scintillators. Each channel has a current-mode input stage (CMIS) followed by a charge sensitive amplifier (CSA). The CMIS is designed for large negative charges and its attenuation can be programmed to be 1, 2.5, 5, 10, or 20. The CMIS input potential is programmable individually for each channel for operation with DC-coupled SiPM/MPPC array readout. The CMIS is ideal for relatively large detector capacitance (several nF) and large detector leakage currents (-10 μA from dark counts). The CMIS can be bypassed to allow for either positive or negative charge directly into the CSA. The CSAs have individually programmable conversion gain of 46, 48, 51, 53, 55 or 265mV/pC. The IC contains one 12-bit analog-to-digital converter (ADC) that allows for digitization of the pulse heights from all channels, including the summing channel at a sampling rate of 2 Msps (FN-about-ADC). Every channel has 2 outputs: one analog output for the pulse height and one digital output for the trigger/timing pulse with fixed width or time-over-threshold. The outputs facilitate many applications, such as external digitization, pulse height and time spectroscopy, pulse counting, triggering, and time-over-threshold. The IC operates at 3.3-V supply voltage and dissipates about 360 mW with both CMIS and on-chip ADC active. To save power, any channel or function can be powered down. The ASIC has a serial peripheral interface (SPI) for programming its register settings and for the readout of ADC and counter data. Fast readout with up to 16 Mbit/s is possible via a serial data transmission line. The IC has been designed to be latch-up immune and resilient to single event upsets.

FN-about-ADC: The ADC data output at TXD_O is not working correctly. We recommend using the chip without the on-chip ADC until the bug is fixed.


The IDE3381 has been designed for high-rate and high-resolution x-ray and γ-ray spectroscopy with scintillators and PMTs or SiPMs.

IDE3381 Simplified block diagram

IDE3381 Simplified block diagram


  • Q. WanY. ZhangJ.H. GuoY.Q. Zhang and X. Xu, 2022, “Design of front-end electronics for HXI spectrometer flight model on-board ASO-S satellite”, Journal of InstrumentationVolume 17February 2022,

Product Features

Detectors SiPM, PMT
Application x-ray and gamma-ray spectroscopy, timing, counting, and imaging
Number of inputs 16 INA, or 17 INB
Input charge range Depends on programmable settings: Max. charge at INA: -40pC, -100pC, -200pC, -400pC, -800pC depending on setting. Max. charge at INB: +/-40pC In addition, 6 fine gain tunings, individual for each channel [mV/pC]: 46, 48, 51, 53, 55, 265
Shaping time Globally programmable: 50ns, 150ns, 300ns, 2000ns
Nominal capacitive load <= several nF at INA <= 100pF at INB
Equivalent Noise Charge (ENC) Depending on shaping time: 7fC at 50ns, 15fC at 150ns, 31fC at 300ns
Trigger threshold 10-bit programmable, individually for each channel
Trigger outputs One global OR from all channels; in addition, each channel has individual trigger output (DOUT)
Outputs Each channel has one analog output (AOUT)
Test and calibration Injection of calibrated charge, or generation of internally calibrated and programable charge
Power consumption 360mW using INA and on-chip ADC; flexible and programmable power-down options
Max event detection rate 1Mcps/channel asynchronous or synchronous
ADC Resolution 12-bit
Data interface SPI for programming and counter readout; ADC serial digital output
Radiation hardness Based on tests with other ASICs designed in the same technology. TID: up to 340 krad(Si) without relevant change; SEL: up to 137 MeV cm2 / mg without latch-up; SEU/SET: LET threshold 18 MeV cm2 / mg or larger
Input voltage range +3.3V