The VATA466 is an application specific integrated circuit (ASIC), which has been designed for the p-side readout of silicon detectors for charged particles. The chip has 36 charge sensitive pre-amplifiers (CSA), programmable coincidence logic and 36 counters, and one analogue multiplexer output. The counters count charge pulses depending on the combination (coincidences or anti-coincidences) and charge magnitude. The counters can be read out from the ASIC by an external controller. Out of the 36 channels, 32 have a high-gain with saturation at 2.6 pC, and 4 have a low gain with saturation at 26 pC. The chip is optimized for positive input charges, i.e., it is suitable for the readout and triggering of the charge from the p-side of silicon sensors.
In the high-gain channels, the charge sensitive pre-amplifier is connected to one slow shaper of 1-μs shaping time and two fast shapers of 250-ns shaping time, while the low-gain channels have only one 1-μs slow shaper and one 250-ns fast shaper. Each fast shaper output is connected to a comparator, which triggers when the pulse shape exceeds the reference level that can be programmed by 10-bit DACs. The two fast shapers and comparators of the high-gain channels are designed to discriminate charges in the range from 2.2 fC to 100 fC and 2.2 fC to 1 pC, respectively. The fast shapers and comparators of the low-gain channels are designed to discriminate charges in the range from 100 fC to 26 pC. Each comparator output is a mono-stable, which can be masked and feeds to the coincidence logic. Read-out of the slow shapers is also possible through a serialised analogue output.
The chip requires positive voltage supplies (+1.8V and +3.3V) and one reference bias current to generate its internal biases. The total power consumption is less than 180 mW, depending on settings and readout rate. The chip has a serial peripheral interface (SPI) for the data readout and programming internal settings. All amplifier inputs are protected by diodes against over-voltage and electro-static discharge (ESD). The chip is SEU/SEL radiation hardened by design and manufacture.
|Number of inputs||36|
|Input charge range||0 fC to 100 fC, 0-2.6 pC, 0-26 pC|
|Shaping time||1 µs (VA), 250ns (TA)|
|Nominal capacitive load||10 pF|
|Equivalent Noise Charge (ENC)||42000e (worst case maximum)|
|Trigger threshold||Programmable by 10-bit DAC|
|Trigger outputs||Common trigger for all channels|
|Outputs||SPI readout of coincidence counters and multiplexed pulse height|
|Test and calibration||Internal calibration circuit|